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[Software Engineering] tut_quartus_intro_schem

Description: this file is a tutorial for schematic in verilog design program
Platform: | Size: 965632 | Author: ahmed | Hits:

[Other] Vending_Machine_using_verilog

Description: This file is full report. Vending machine of verilog HDL for soft drink are provide in this file.-Vending Machine is a soft drink dispensor machine that dispenses drink based on the amount deposited in the machine.
Platform: | Size: 111616 | Author: anthonykang | Hits:

[VHDL-FPGA-Verilog] FPGA_SDRAM

Description: FPGA对SDRAM的控制操作源码,用VERILOG硬件描述语言编写,包含的文件一共有:hostcont.v,inc.h,pinouts.ucf,sdram.v,top.v,tst_inc.h-Control of operation of the SDRAM FPGA source code, using VERILOG hardware description language, the file contains a total of: hostcont.v, inc.h, pinouts.ucf, sdram.v, top.v, tst_inc.h
Platform: | Size: 21504 | Author: 陈维 | Hits:

[Other] leftrightleds

Description: 流水灯模块的Verilog实现附带完整的测试文件-Verilog realization of water lamp module with a complete test file
Platform: | Size: 437248 | Author: fqzxw | Hits:

[Windows Develop] language

Description: vhdl语言集锦 VHDL是Very High Speed Integrated Circuit Hardware Description Language的缩写,意思是超高速集成电路硬件描述语言。对于复杂的数字系统的设计,它有独特的作用。它的硬件描述能力强,能轻易的描述出硬件的结构和功能。这种语言的应用至少意味着两种重大的改变：电路的设计竟然可以通过文字描述的方式完成；电子电路可以当作文件一样来存储。随着现代技术的发展,这种语言的效益与作用日益明显,每年均能够以超过30 的速度快速成长。-VHDL language VHDL is an abbreviation for “Very High Speed Integrated Circuit Hardware Description Language”. and is along with Verilog the most widely used hardware description language. It is used to describe the behavior and structure of electronic systems, but is particularly suited as a language to describe the structure and behavior of digital electronic hardware designs. The application of it means two changes: electro circuit design can be done by the kind of file description. and electro circuit can be stored as a file.
Platform: | Size: 173056 | Author: zhanglingxiang | Hits:

[VHDL-FPGA-Verilog] decoder3_8

Description: 这是个三八译码器的文件，里面的程序是VERILOG语言编写的，很适合初学者使用-This is a file decoder 38, which the program is written in VERILOG, it is suitable for beginners
Platform: | Size: 1052672 | Author: maohuhua | Hits:

[VHDL-FPGA-Verilog] decoder38

Description: 这是个译码器的文件，里面的程序是VERILOG语言编写的，很适合初学者使用-This is a file decoder, which the program is written in VERILOG, it is suitable for beginners
Platform: | Size: 154624 | Author: maohuhua | Hits:

[VHDL-FPGA-Verilog] led

Description: 这是个灯闪烁的文件，里面的程序是VERILOG语言编写的，很适合初学者使用-This is a light flashing file, which the program is written in VERILOG, it is suitable for beginners
Platform: | Size: 130048 | Author: maohuhua | Hits:

[Other] synopsys_VCS_TOOL_flow

Description: this pdf file will gives the details of synopsys tool design space and verilog HDL ASIC design based tips.also this pdf is a power point presentation with functional verification tool of synopsys VCS tool.... VERY USEFULL FOR PROFESSORS
Platform: | Size: 2502656 | Author: jithin kumar M V | Hits:

[VHDL-FPGA-Verilog] Desktop

Description: it s a file contain Verilog code of a full adder. I hope this file is usefull for someone ! Regards !
Platform: | Size: 3072 | Author: yuri katachi | Hits:

[VHDL-FPGA-Verilog] processor

Description: 文件中包含一个简单MIIPS CPU的Verilog源代码-File contains a simple MIIPS CPU in Verilog source code
Platform: | Size: 95232 | Author: wangboch | Hits:

[VHDL-FPGA-Verilog] in-ModelSim-and-Xilinx-lib

Description: 在ModelSim SE中配置Xilinx的库函数 在Modelsim的安装根目录下新建一个文件夹，用来放xilinx的各个库文件，故可以起名 xilinx_lib。类似于Xinlinx的安装文件：\..\\Xilinx\verilog\src中的各个库文件，在xilinx_lib文件 下新建各个文件夹，命名规则为：若src中的文件夹名为unisims，则在xilinx_lib文件夹下新建 为unisims_ver的文件夹，与此雷同，新建名为simprims_ver、XilinxCoreLib_ver、iSE_ver unisims_ver的各个文件夹。 -ModelSim SE configured in the library function in Modelsim Xilinx installation root directory create a new folder to put all the library files xilinx, it can be named xilinx_lib. Similar Xinlinx installation file: \ .. \ \ Xilinx \ verilog \ src in the various libraries in New xilinx_lib each folder under the file named rule: If the src folder named unisims, the file in the xilinx_lib new folder under the folder for the unisims_ver, and this similarity, the new name simprims_ver, XilinxCoreLib_ver, iSE_ver unisims_ver each folder.
Platform: | Size: 106496 | Author: 谢明 | Hits:

[VHDL-FPGA-Verilog] chengxushejiyuyingjianshixian

Description: 此文件包含了一系列关于Verilog VHDL环境下的程序设计与硬件实现。-This file contains a series of procedures under Verilog VHDL design and hardware implementation.
Platform: | Size: 657408 | Author: Joanna999 | Hits:

[VHDL-FPGA-Verilog] Xilinx

Description: Demux modules and test simulations with various combinations of input and output vectors.I am new to Verilog.I am learning it through a electronic system design course on my college.I am interested in downloading a single .zip file from this site,Verilog code for MAC data layer protocol.I hope you will consider my request.
Platform: | Size: 5120 | Author: Igor | Hits:

[VHDL-FPGA-Verilog] VGA_FPGA

Description: 我用FPGA verilog语言写的VGA显示程序，是我做的一个课程设计，在显示器上显示我的学号20082831.当然也可以改的，里面有三个文件，一个是头文件。-FPGA verilog language written with VGA display program, I do a course design, displayed on the monitor my student number 20082831. Of course, can be changed, there are three files, one header file.
Platform: | Size: 400384 | Author: 张亮 | Hits:

[VHDL-FPGA-Verilog] clock_norst

Description: 时钟显示，verilog 代码，时钟实现没有使用复位信号，带测试文件-Clock display, verilog code, the clock to achieve without the use of a reset signal, with the test file
Platform: | Size: 1024 | Author: 张恒 | Hits:

[VHDL-FPGA-Verilog] water

Description: 一个verilog编写的流水灯例程，包含整个工程及下载文件-Written in a light water verilog routines, including the entire project and download the file
Platform: | Size: 159744 | Author: | Hits:

[ELanguage] VCDdecoder

Description: 基于GTK-wave做的verilog　test bench语法解析器 解析vcd file. 俺自己写的-VCD (Value Change Dump) file is widely used in industry. A VCD file is an ASCII file, which contains header information, variable definitions and the value changes for specified variables, or all variables, in a given design. Attached VCD_format.pdf gives a simple introduction to VCD file format. More information about VCD file format can be found in Web. Please write a tool to parse a VCD file. It reads in the VCD file specified in the command line, counts the value changes for each variable and output a file which states the name and counts for value change low-to-high and high-to-low for each variable. A example VCD file is also attached for testing purpose. RULES: 1. $date, $version, $comment and $dump* can be ignored 2. Output file name is <design_name>.toggle, where design_name is the topmost module name in the VCD file. For example, if the 1st $scope line in the file: $scope module AAA_tmax_testbench_1_16 $end the output file name should be AAA_tmax_t
Platform: | Size: 8051712 | Author: Hao Wang | Hits:

[VHDL-FPGA-Verilog] acc32bit

Description: 本设计为32位数字相位累加器，门级描述的Verilog代码。其中，acc32bit.v为顶层文件，full_add1.v为一位全加器的门级描述模块，flop.v为触发器的门级描述模块。-The design for the 32-bit digital phase accumulator, gate-level description of the Verilog code. Which, acc32bit.v as top-level file, full_add1.v as a full adder gate-level description module, flop.v to trigger the gate-level description of the module.
Platform: | Size: 755712 | Author: 吴亮 | Hits:

[VHDL-FPGA-Verilog] sd

Description: 一个基于verilog的数码相框的实现,全是verilog写的,里面包括一个sd驱动的文件系统-Verilog-based implementation of digital photo frame, all written in verilog, which includes a file system driver sd
Platform: | Size: 10806272 | Author: jibaozhang | Hits:
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